The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor device having separate hard masks formed from common material to facilitate sidewall image transfer (SIT) block patterning.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as field effect transistors (FETs) and on-chip capacitors, are fabricated on a single wafer. Some non-planar device architectures, such as vertical field effect transistors (VFETs), employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. There are challenges, however, in providing non-planar architectures for scaling beyond the 10 nm node. One technique for increasing device density is to double spacer pattern density through a technique called sidewall image transfer (SIT), also known as sidewall spacer image transfer.